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DATA SHEET
MOS INTEGRATED CIRCUIT
PD3768
7500 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR
DESCRIPTION
The PD3768 is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The PD3768 has 3 rows of 7500 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge transfer register, which transfers the photo signal electrons of 7500 pixels separately in odd and even pixels. Therefore, it is suitable for 600 dpi/A3 high-speed color digital copiers, color scanners and so on.
FEATURES
* Valid photocell * Photocell pitch * Line spacing * Color filter * Resolution * Data rate * Output type * Power supply * On-chip circuits : 7500 pixels x 3 : 9.325 m : 37.3 m (4 lines) Red line - Green line, Green line - Blue line : Primary colors (red, green and blue), pigment filter (with light resistance 10 lx*hour) : 24 dot/mm A3 (297 x 420 mm) size (shorter side) : 44 MHz MAX. (22 MHz/1 output) : 2 outputs in phase/color : +10 V : Reset feed-through level clamp circuits Voltage amplifiers
7
* Drive clock level : CMOS output under 5 V operation
ORDERING INFORMATION
Part Number Package CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600))
PD3768D
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S15418EJ2V0DS00 (2nd edition) Date Published September 2002 NS CP (K) Printed in Japan
The mark
shows major revised points.
2001
PD3768
BLOCK DIAGRAM
CP 2L
20
GND 16
1B
2A
30
29
28
23
24
VOD
31
VOUT2 (Blue, even)
32
D128
CCD analog shift register Transfer gate
S7499 S7500 D129 D140
D27
GND VOUT1 (Blue, odd) GND
33
.....
S1 S2
Photocell (Blue)
.....
22
TG1 (Blue)
34 35
Transfer gate CCD analog shift register
VOUT3 36 (Green, odd)
D128 D27
CCD analog shift register Transfer gate
S7499 S7500 D129 S1 S2
.....
.....
D140
Photocell (Green)
21
TG2 (Green)
VOUT4 1 (Green, even) GND VOUT6 (Red, even) 2 3
D128
Transfer gate CCD analog shift register
CCD analog shift register Transfer gate
S7499 S7500 D129 S1 S2 D140
D27
GND
4
.....
Photocell (Red)
.....
15
TG3 (Red)
VOUT5 (Red, odd)
5
Transfer gate CCD analog shift register
6 VOD
7
R
8
2L
9
10
13
1A
14
2B
2
Data Sheet S15418EJ2V0DS
PD3768
PIN CONFIGURATION (Top View)
CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600)) * PD3768D
Output signal 4 (Green, even) VOUT4 1 Ground GND 2
36 VOUT3 35 GND
Output signal 3 (Green, odd) Ground Output signal 1 (Blue, odd) Ground Output signal 2 (Blue, even) Output unit drain voltage Reset feed-through level clamp clock Last stage shift register clock Shift register clock 20
1
1
Output signal 6 (Red, even) VOUT6 3 Ground GND 4
1 Blue
34 VOUT1 33 GND 32 VOUT2 31 VOD 30 CP 29 2L 28 20
Output signal 5 (Red, odd) VOUT5 5 Output unit drain voltage Reset gate clock Last stage shift register clock Shift register clock 10 VOD 6
R 7 2L 8
10 9
No connection No connection No connection Shift register clock 1A Shift register clock 2B
Green
Red
NC 10 NC 11 NC 12
27 NC 26 NC 25 NC 24 2A 23 1B 22 TG1
No connection No connection No connection Shift register clock 2A Shift register clock 1B Transfer gate clock 1 (for Blue) Transfer gate clock 2 (for Green) No connection No connection
1A 13 2B 14
Transfer gate clock 3 (for Red) TG3 15
7500
7500
7500
Ground No connection No connection
GND 16 NC 17 NC 18
21 TG2 20 NC 19 NC
Caution
Connect the No connection pins (NC) to GND.
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)
9.325 m 6.325 m 3 m Channel stopper 9.325 m
Blue photocell array 4 lines (37.3 m) Green photocell array 4 lines (37.3 m)
Aluminum shield
9.325 m
9.325 m
Red photocell array
Data Sheet S15418EJ2V0DS
3
PD3768
ABSOLUTE MAXIMUM RATINGS (TA = +25C)
Parameter Output drain voltage Shift register clock voltage Last gate shift register clock voltage Reset gate clock voltage Clamp clock voltage Transfer gate clock voltage Operating ambient temperature Note Storage temperature VOD V 1, V 2 V 2L V R V CP V TG1 to V TG3 TA Tstg Symbol Ratings -0.3 to +12 -0.3 to +8 -0.3 to +8 -0.3 to +8 -0.3 to +8 -0.3 to +8 -25 to +60 -40 to +100 Unit V V V V V V C C
Note Use at the condition without dew condensation. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25C)
Parameter Output drain voltage Shift register clock high level Shift register clock low level Last gate shift register clock high level Last gate shift register clock low level Reset gate clock high level Reset gate clock low level Clamp clock high level Clamp clock low level Transfer gate clock high level Transfer gate clock low level Data rate VOD V 1H, V 2H V 1L, V 2L V 2LH V 2LL V RH V RL V CPH V CPL V TG1H to V TG3H V TG1L to V TG3L 2f R Symbol Min. 9.5 4.5 -0.3 4.5 -0.3 4.5 -0.3 4.5 -0.3 4.5 -0.3 1 Typ. 10.0 5.0 0 5.0 0 5.0 0 5.0 0
Note V 1H
Max. 10.5 5.5 +0.5 5.5 +0.5 5.5 +0.5 5.5 +0.5
Note V 1H
Unit V V V V V V V V V V V MHz
0 2
+0.5 44
Note When Transfer gate clock high level (V TG1H to V TG3H) is higher than Shift register clock high level (V 1H), Image lag can increase.
4
Data Sheet S15418EJ2V0DS
PD3768
ELECTRICAL CHARACTERISTICS
TA = +25C, VOD = 10 V, f R = 1 MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 Vp-p, light source (except Response1) : 2950 K halogen lamp + CM-500S (infrared cut filter, t = 1 mm)
Parameter Saturation voltage Saturation exposure Red Green Blue Photo response non-uniformity Photo response non-uniformity at low illumination Average dark signal ADS Light shielding, data rate = 2 MHz, storage time = 10 ms Dark signal non-uniformity DSNU Light shielding, data rate = 2 MHz, storage time = 10 ms Power consumption Output impedance Response1 Red Green Blue Response2 Red Green Blue Image lag Image lag color difference Image lag O/E Offset level
Note 1 Note 2
Symbol Vsat SER SEG SEB PRNU PRNU2
Test Conditions 2950 K halogen lamp + CM-500S
Min. 1.5 - - - - - - - - -
Typ. 2.0 0.14 0.13 0.26 6.0 6.0
Max. - - - - 18.0 18.0
Unit V lx*s lx*s lx*s % %
VOUT = 1.0 V VOUT = 0.1 V
1.0
5.0
mV
3.0
12.0
mV
PW ZO RR RG RB RR RG RB IL IL-DIF IL-O/E VOS td RI TTE Red Green Blue VOUT = 1.0 V VOUT = 1.0 V, f R = 22 MHz VOUT = 500 mV VOUT = 500 mV VOUT = 500 mV 2950 K halogen lamp + CM-500S 3200 K halogen lamp + C-500S + HA-50
700 0.2 22.0 18.0 8.0 14.0 15.3 7.6 40 5 10 4.5 14 0 98 630 540 445 666 870 -200 2.3
900 0.4 28.6 23.4 10.4 18.2 19.9 9.9 80 20 30 5.2 - 5 - - - - - - +500 -
mW k V/lx*s V/lx*s V/lx*s V/lx*s V/lx*s V/lx*s mV mV mV V ns % % nm nm nm times times mV mV
15.4 12.6 5.6 9.8 10.7 5.3 - - - 3.8 - - 94 - - - - - -1000 -
Output fall delay time Register imbalance
Total transfer efficiency Response peak
Dynamic range
DR1 DR2
Vsat/DSNU Vsat/ dark Light shielding Bit clamp, t17 = 10 ns
Reset feed-through noise Light shielding random noise
RFTN
dark
Notes 1. Refer to TIMING CHART 2 and TIMING CHART 4. 2. td is defined as periods from 10% of 2L to 10% of VOUT1 to VOUT6 (refer to APPLICATION CURCUIT EXAMPLE).
Data Sheet S15418EJ2V0DS
5
PD3768
INPUT PIN CAPACITANCE (TA = +25C, VOD = 10 V)
Parameter Shift register clock pin capacitance Symbol C 1 Pin Pin No. 9 13 23 14 24 28 8 29 Reset gate clock pin capacitance Clamp clock pin capacitance Transfer gate clock pin capacitance C R C CP C TG Min. - - - - - - - - - - - - - Typ. 330 330 330 330 330 330 10 10 10 10 100 100 100 Max. 450 450 450 450 450 450 20 20 20 20 150 150 150 Unit pF pF pF pF pF pF pF pF pF pF pF pF pF
10 1A 1B 2B 2A 20 2L R CP TG1 TG2 TG3
C 2
Last stage shift register clock pin capacitance
C L
7 30 22 21 15
6
Data Sheet S15418EJ2V0DS
TIMING CHART 1 (Bit clamp mode, for each color)
TG1 to TG3
10, 1A, 1B
20, 2A, 2B
2L
R
Data Sheet S15418EJ2V0DS
CP
7625 7627 7629 7631 7633 7635 7637
Note
119 121 123 125 127 129 131 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
Note
VOUT1, 3, 5
VOUT2, 4, 6
Optical black (96 pixels)
Valid photocell (7500 pixels)
Invalid photocell (6 pixels)
7626 7628 7630 7632 7634 7636 7638
120 122 124 126 128 130 132
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
Invalid photocell (6 pixels)
PD3768
Note Set the R and CP pulse to low level during this period.
7
PD3768
TIMING CHART 2 (Bit clamp mode, for each color)
t6 t7
10, 1A, 1B 20, 2A, 2B
t7L t6L
90% 10% 90% 10%
2L
90% 10% t8 90% 10%
t9 t10 t17
t15
R
t16 t12 t13
t14
CP
90% 10% td
+ RFTN -
VOUT1 to VOUT6 10%
VOS
Symbol t6, t7 t6L, t7L t8, t10 t9 t12, t14 t13 t15 t16 t17
Min. 0 0 0 10 0 10 0 8 8
Typ. 50 5 5 125 5 125 250 125 125
Max. - - - - - - - - -
Unit ns ns ns ns ns ns ns ns ns
8
Data Sheet S15418EJ2V0DS
TIMING CHART 3 (Line clamp mode, for each color)
TG1 to TG3
10, 1A, 1B 20, 2A, 2B
2L
R
Data Sheet S15418EJ2V0DS
CP
7625 7627 7629 7631 7633 7635 7637
Note
119 121 123 125 127 129 131 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
Note
VOUT1, 3, 5
VOUT2, 4, 6
Optical black (96 pixels)
Valid photocell (7500 pixels)
Invalid photocell (6 pixels)
7626 7628 7630 7632 7634 7636 7638
120 122 124 126 128 130 132
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
Invalid photocell (6 pixcels)
PD3768
Note Set the R and CP pulse to low level during this period.
9
PD3768
TIMING CHART 4 (Line clamp mode, for each color)
t6 t7
10, 1A, 1B 20, 2A, 2B
t7L t6L
90% 10% 90% 10%
2L
90% 10% t8 90% 10%
t9
t10
t20
R
CP
'L' td
+ RFTN -
VOUT1 to VOUT6 10%
VOS
Symbol t6, t7 t6L, t7L t8, t10 t9 t20
Min. 0 0 0 10 5
Typ. 50 5 5 125 250
Max. - - - - -
Unit ns ns ns ns ns
10
Data Sheet S15418EJ2V0DS
PD3768
TIMING CHART 5 (Bit clamp mode, line clamp mode, for each color)
t2 t3 t4
TG1 to TG3
90% 10% t1 90%
10, 1A, 1B 20, 2A, 2B
2L
Note t5 90% 10% t16 t12 t13 t14 t8 t9 t10 t17 t15
R
CP
90% 10%
Symbol t1, t5 t2, t4 t3 t8, t10 t9 t12, t14 t13 t15 t16 t17
Min. 200 0 3000 0 10 0 10 0 8 8
Typ. 300 50 5000 5 125 5 125 250 125 125
Max. - - - - - - - - - -
Unit ns ns ns ns ns ns ns ns ns ns
Note Set the R and CP pulse to low level during this period.
Data Sheet S15418EJ2V0DS
11
PD3768
10, 20 cross points
10
2.0 V or more 2.0 V or more
20
1A, 2A cross points
1A
2.0 V or more 2.0 V or more
2A
1B, 2B cross points
1B
2.0 V or more 2.0 V or more
2B
10, 2L cross points
10
2.0 V or more 0.5 V or more
2L
Remark Adjust cross points ( 10, 20), ( 1A, 2A), ( 1B, 2B) and ( 10, 2L) with input resistance of each pin.
12
Data Sheet S15418EJ2V0DS
PD3768
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula, and it is defined by each six of them.
x
x x 100
PRNU (%) =
x : maximum of xj - x
7500 j=1
xj
7500
x=
xj : Output voltage of valid pixel number j
VOUT
Register Dark DC level
x
x
4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula, and it is defined by each six of them.
7500 j=1
dj
7500 dj : Dark signal of valid pixel number j
ADS (mV) =
Data Sheet S15418EJ2V0DS
13
PD3768
5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula, and it is defined by each six of them.
DSNU (mV) : maximum of dj - ADS j = 1 to 7500 dj : Dark signal of valid pixel number j
VOUT ADS Register Dark DC level DSNU
6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx*s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line.
TG
Light ON OFF
VOUT V1 VOUT
IL (mV) = V1
(VOUT = 500 mV)
9. Image lag color difference : IL-DIF It is defined as a difference between colors of the average of image lag. It is expressed with the next expression to be concrete.
| (average of image lag of blue output) - (average of image lag of green output) | | (average of image lag of green output) - (average of image lag of red output) | | (average of image lag of red output) - (average of image lag of blue output) |
14
Data Sheet S15418EJ2V0DS
PD3768
10. Image lag O/E : IL-O/E It is defined as a difference of the average of image lag of odd and even pixels for each color. 11. Register imbalance : RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels.
n
2 n RI (%) =
j=1
(V2j -1 - V2j)
1 n
j=1
2
Vj
n : Number of valid pixels Vj : Output voltage of each pixel
n
x 100
12. Total transfer efficiency : TTE The total transfer rate of CCD analog shift register. This is calculated by the following formula, it is difined by each output. TTE (%) = (1 - Vb / average output of all the valid pixels) x 100
Vb Va-1 : The last pixel output - 1 (Odd pixel: 7631th pixel) Va : The last pixel output (Odd pixel: 7633th pixel) Vb : The spilt pixel output (Odd pixel: 7635th pixel) Va-1 Va
13. Light shielding random noise : dark Light shielding random noise dark is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding).
100
dark (mV) =
i=1
(Vi - V)
100
2
, V=
1
100
100 i = 1
Vi
Vi : A valid pixel output signal among all of the valid pixels for each color
V1 V2
...
VOUT
line 1 line 2
...
V100
line 100
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).
Data Sheet S15418EJ2V0DS
15
PD3768
STANDARD CHARACTERISTIC CURVES (Reference Value)
DARK OUTPUT TEMPERATURE CHARACTERISTIC
8 2
STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25C)
4
Relative Output Voltage Relative Output Voltage
1
2
1
0.5
0.25
0.2
0.1 0
10
20
30
40
50
0.1
1
5 Storage Time (ms)
10
Operating Ambient Temperature TA (C)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (TA = +25C)
100 R
80 G
Response Ratio (%)
60
B
40
20
B
G 0 400 500 Wavelength (nm) 600 700
16
Data Sheet S15418EJ2V0DS
PD3768
APPLICATION CIRCUIT EXAMPLE
+5 V 10 +
B4
+10 V
PD3768
1 2 3
B6
+ 36 35 34 33 32 31 30 29 28 47 47 2
B2 B1 B3
10 F/16 V 0.1 F
VOUT4 GND VOUT6 GND VOUT5 VOD
VOUT3 GND VOUT1 GND
VOUT2
0.1 F 47 F/25 V
+5 V
4
B5
+
5 6
0.1 F 10 F/16 V
R
47 47 2
VOD
7 8 9
R 2L 10
CP
CP 2L 20
2L 10
2L 20
10 11
NC NC NC
NC NC NC
27 26 25 24 23 22 21 20 19 2 2 2 2
1A
2
12 13
2A
2B
2 2
1A 2B TG3
GND NC NC
2A
1B TG1 TG2
NC NC
14 15 16 17 18
1B TG1 TG2
TG3
Caution Connect the No connection pins (NC) to GND. Remarks 1. Connect two inverters (74AC04) to each 10, 1A, 1B, 20, 2A, 2B pin. 2. Inverters shown in the above application circuit example are the 74AC04. 3. B1 to B6 in the application circuit example are shown in the figure below.
B1-B6 equivalent curcuit +10 V 47 F/25 V + 4.7 k 110 CCD VOUT 47 2SA1005 1 k 2SC945
Data Sheet S15418EJ2V0DS
17
PD3768
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 36-PIN CERAMIC DIP (15.24 mm (600))
94.00.7 3.00.1 1.280.1 3.000.08 1.00.08
4
26.00.2 33.30.6 The 1st valid pixel
1
7.330.3
(5.0) 1.27 (2.6)
3
14.66
3.850.38 (1.8)
24.130.20 20.320.13 48.260.40
0.46 20.320.13 2.540.13 2.00.2 5.00.2 2.40.3
2
(17.09 MAX.) (15.24 MIN.)
0.250.05
Name Glass cap
Dimension 91.0x9.0x1.1
Refractive index 1.5
1 1st valid pixel
Center of package The surface of the chip The surface of the glass cap
2 The bottom of package 3 The surface of the chip
4 The tolerance of packge dimension 0.25 : less than 10 mm from W/F edge 0.50 : equal or more than 10 mm from W/F edge 36D-1CCD-PKG3-1
18
Data Sheet S15418EJ2V0DS
PD3768
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. Type of Through-hole Device
PD3768D : CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600))
Process Partial heating method Conditions Pin temperature : 300 C or below, Heat time : 3 seconds or less (per pin)
Cautions 1. During assembly care should be taken to prevent solder or flux from contacting the glass cap. The optical characteristics could be degraded by such contact. 2. Soldering by the solder flow method may have deleterious effects on prevention of glass cap soiling and heat resistance. So the method cannot be guaranteed.
Data Sheet S15418EJ2V0DS
19
PD3768
NOTES ON HANDLING THE PACKAGES
1 MOUNTING OF THE PACKAGE
The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with glass cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating For this product, the reference value for the three-point bending strength Note is 180 [N] (at distance between supports: 70 mm), is 500 [N] (at distance between supports: 26 mm). Avoid imposing a load, however, on the inside portion as viewed from the face on which the window (glass) is bonded to the package body (ceramic). Note Three-point bending strength test Distance between supports: 70 mm or 26 mm, Support R: R 2 mm, Loading rate: 0.5 mm/min. Load Load
70 mm
70 mm
Load
Load
26 mm
26 mm
2 GLASS CAP
Don't either touch glass cap surface by hand or have any object come in contact with glass cap surface. Care should be taken to avoid mechanical or thermal shock because the glass cap is easily to damage. For dirt stuck through electricity ionized air is recommended.
20
Data Sheet S15418EJ2V0DS
PD3768
NOTES ON HANDLING THE PACKAGES
3 OPERATE AND STORAGE ENVIRONMENTS
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
4 ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. 2. 3. 4. 5. Ground the tools such as soldering iron, radio cutting pliers of or pincer. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. Either handle bare handed or use non-chargeable gloves, clothes or material. Ionized air is recommended for discharge when handling CCD image sensor. For the shipment of mounted substrates, use box treated for prevention of static charges.
6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 M.
Data Sheet S15418EJ2V0DS
21
PD3768
[ M E MO ]
22
Data Sheet S15418EJ2V0DS
PD3768
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S15418EJ2V0DS
23
PD3768
* The information in this document is current as of September, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4

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